High Performance Integrated Circuit Design. Communications Receivers, Fourth Edition. Advanced Circuits for Emerging Technologies. Introduction to Mixed-Signal, Embedded Design. Circuit Design for Reliability. Ultra-thin Chip Technology and Applications. Voltage Regulators for Next Generation Microprocessors. Cognitive Radio Receiver Front-Ends. Antonio Carlos Schneider Beck. Energy and Bandwidth-Efficient Wireless Transmission. Winning the SoC Revolution. Distributed, Embedded and Real-time Java Systems. High-Speed Clock Network Design.
Scalable Techniques for Formal Verification. Millimeter-Wave Low Noise Amplifiers. Automotive Radar Sensors in Silicon Technologies. Virtual Components Design and Reuse. Cloud Connectivity and Embedded Sensory Systems. Design for Reliability, Security, and Low Power. Bandpass Sigma Delta Modulators. How to write a great review. The review must be at least 50 characters long. The title should be at least 4 characters long.
Your display name should be at least 2 characters long. At Kobo, we try to ensure that published reviews do not contain rude or profane language, spoilers, or any of our reviewer's personal information. You submitted the following rating and review. We'll publish them on our site once we've reviewed them. Extensive measurements over different modes show a consistent improved IIP2 performance beyond 60 dBm, which is enough to cope with the toughest FDD cellular requirements.
The RX analog baseband can be separately tested thanks to on-chip test circuitry that allows providing an external input signal to the TIA input. From a 2-port network analyzer measurement, the several transfer function settings are shown in Fig. Power consumption scales with the bandwidth from 16 to 28 mW: The influence of baseband DC offset is negligible in both these tests. The ADC is measured separately, as reported in Fig. At lower speeds, the power decreases proportionally. Using the classical figure- 26 J.
Fs , a value of 34 f J per conversion step is obtained. One of the unique features of an SDR transceiver is its energy awareness: On top of such standard- related trade-offs, it is also possible to provide run-time energy awareness by sensing the environmental conditions. Blockers could for example be sensed by adding power detectors at various filtering stages in the receive chain, SNR could for example be sensed to tune the receiver to a 'minimal margin' scenario.
To exemplify this, Fig. Or receiving in the countryside is likely not to impose the toughest blocking conditions foreseen by the standards. An 8-PSK modulated signal up to 4.
The CNR was measured in two ways. First, a single tone was transmitted by applying a DC signal at baseband, and a phase-noise analyzer was used to determine the noise floor of the transmitter. The main noise contributor in this mode is baseband noise from the active filter, which is not filtered by the passive pole, due to its relatively high cut-off frequency. The TX band signal was filtered by a reversed duplexer transmitter at output port , and the noise at the RX port in the receive band was measured, after de-embedding of the duplexer's insertion loss. It is caused by the jitter introduced by the limited relative speed of the LO signal's edges.
At MHz, the limitation comes from the baseband noise due to the smaller 45 MHz offset between TX and RX band and the resulting reduced filtering from the passive pole and the active second order filter. The power consumption of the transmitter varies with the required performance. This prototype once again shows that SDR platforms in nanoscale CMOS technologies are the preferred implementation choice for future ubiquitous mobile terminals.
Van der Perre, J. Van Wesemael, and J. Communications ICC , , pp. Van Wesemeal, and J. Liu, T Wang, and S. V Giannini et al. European Solid-State Circuits Conf. T Sowlati et al. On the receiver RX path, the signal from an antenna is filtered by a typically-external bandpass filter BPF to attenuate out- of-band blockers. The signal is then amplified by a low-noise amplifier LNA and downconverted i.
The digital baseband processes the signal samples to estimate the original transmitted symbols, from which the user information data is obtained. On the transmitter TX path, the user information data gets converted into sym- bols, which are then pulse-shaped to obtain baseband I and Q digital samples that are frequency-band-constrained. Thus obtained analog baseband signal gets then upconverted frequency translated into RF through an image-reject single- sideband SSB modulator.
An example of a TX digital polar modulator is shown in Fig. The phase modulation could be performed by a direct or indirect frequency modulation of a phase-locked loop PLL. The amplitude modulation could be performed by Vod modulation of a high-efficiency class-E PA. It is typically realized as a charge-pump PLL [2] with EA dithering of the modulus divider to realize the fractional-Af frequency division ratio. The architecture has been successfully used in integrated CMOS transceivers [5] for over a decade since late s. Unfortunately, its useful lifetime is slowly coming to an end [6] in favor of more digitally-intensive architectures, such as the one shown in Fig.
Basically, with every CMOS process technology advancement node i. At the same time, the basic gate delay, being a measure of the digital processing speed, improves linearly i. Likewise, the cost of fabricated silicon per unit area remains roughly the same at its high-volume production maturity stage.
The main implication of this is that a cost of a given digital function, such as a GSM detector or an MP3 decoder, can be cut in half every 1 months when transitioned to a newer CMOS technology. At the same time, the circuits consume proportionately less power and are faster. Unfortunately, these wonderful benefits of the digital scaling are not shared by the traditional RF circuits. What's more, the strict application of the Fig. The constant scaling of the CMOS technology has had an unfortunate effect on the linear capabilities of analog transistors.
To maintain reliability of scaled-down MOS devices, the Vdd supply voltage keeps on going down, while the threshold voltage V t remains roughly constant to maintain the leakage current. This has a negative effect on the available voltage margin when the transistors are intended to operate as current sources. Furthermore, due to the thin gate dielectric becoming ever thinner, large high- density capacitors realized as MOS switches are becoming unacceptably leaky. This prevents an efficient implementation of low-frequency baseband filters and charge- pump PLL [2] loop filters.
The raw analog performance, which is based on the traditional linear transistor operation, keeps on getting worse with each CMOS process node advancement in almost every aspect. On the other hand, the raw digital capability, in terms of processing sophistication and speed, is improving. An interesting question is whether the new powerful, yet inexpensive, digital logic and memory can compensate through well-known techniques such as calibration, compensation and predistortion for the increasing handicap of analog performance.
The unfortunate answer is generally "no". The raw performance degradation of RF circuits is much worse than the assistance the digital processing can offer. The chief reason for this negative answer is the sheer complexity of the transceiver component interaction. While it might be possible in an isolated case to calibrate or compensate for single parameter degradation, a degraded component typically affects multitude of parameters, which are very difficult or even impossible, within a given processing budget, to simultaneously calibrate. All these three system imperfections contribute to the signal distortion in a way that is difficult to isolate from each other.
This makes the calibration algorithm disproportionately more complex or even unfeasible. A quick survey of the most recent literature reveals no such impending doom and gloom. In fact, the RF performance of highly integrated system-on-chip SoC 's actually keeps on improving. The reason for this apparent paradox is the changing nature of the RF circuit design. Just like it has happened with the analog audio processing in the s and s, when new digitally-intensive techniques oversampling, EA noise shaping, calibration, etc. Arguably, the first demonstrations of the new all-digital approaches to RF [7, 8] 3 Digital RF and Digitally-Assisted RF 39 were so revolutionary that they must have been perceived as threatening enough to the traditionally-minded RF design community, such that a frantic search for more evolutionary alternatives has been spurred.
Even though the new Digital RF approach is now dominant in mobile phones, the analog-intensive alternatives still exist. However, their nature has been changed forever. To put this into proper perspective: The design of RF circuits in any type of CMOS around the year was so uncommon in industry that it was generally met with incredulity and derision, and it took a few prominent researchers in academia [5, 9] to gradually change that negative perception. On top of that, our desire was not only to use CMOS for RF circuit design but rather its most advanced digital version for the purpose of single-chip radio integration.
This general atmosphere of ignorance, negativity and avoidance outside of our immediate group has given us enough head start and secure a few years of development advantages. Our early attempt at designing RF circuits in advanced CMOS has made it clear that we were facing a new paradigm, which has allowed us to form a foundation of a new area of electronics: The new paradigm was first formulated in the author's Ph. In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals.
Nowadays, with only 1. Hence, the information can be tracked and processed as timestamps of sharp transitions between Vss an d Vdd- Figure 3. The increasing level of noise makes the voltage resolution AV worse. Trimming, heavily used in precision analog IC's, can bring down these tolerances to the 0. At the same time, a mixed-signal IC would typically contain a crystal-stabilized reference clock with the tolerance of ppm parts per million , which is orders of magnitude better.
This is another argument for moving towards the time-domain operation. Despite the early misconceptions that the digitalization of RF would somehow produce more phase noise, spurs and distortion, the resulting digitally-intensive architecture is likely to be overall more robust by actually producing lower phase noise and spurious degradation of the transmitter chain and lower noise figure of the receiver chain in face of millions of active logic gates on the same silicon die, as repeatedly proven in subsequent publications [7, 8, 12, 13].
Additionally, the new architecture would be highly reconfigurable with analog blocks that are controlled by software to guarantee the best achievable performance and parametric yield. Another benefit of the new architecture would be an easy migration from one process node to the next without significant rework. They all came from commercial efforts involving large design teams so a reasonable effort to reduce area and power can be assumed. Its silicon area was 40 mm 2 in nm CMOS.
It was a significant commercial endeavor but, to the author's best knowledge, the chip never went into volume production. The third published RF-SoC and the first one targeting a cellular standard, was in from Infineon [15]. Remarkably, there is no mention of any digital assistance and the overall impression is that the RX-DBB integration exercise was rather hurried, thus giving little time to exploit the synergy.
The silicon area is 24mm 2 in 90 nm CMOS, 3. In the same year of , there were two other disclosures, both from Atheros and both using nm CMOS. The silicon area is 9. The frequency synthesizer comprising the LO is build using a charge-pump PLL in which the fractional frequency resolution is obtained through EA dithering of the modulus divider.
The transmitter is either analog IIQ or analog polar topology, while the receiver is a typical continuous-time mixer-based architecture. All of them, however, disclose employment of the digital assistance of RF except for [15]. The analog-intensive approaches, however, do not fully benefit from scaling. Non-cellular wireless applications require less stringent RF performance but the lower supply voltage of core transistors appears to be achievable only with Bluetooth, which is considered the least demanding of all popular standards.
As no publications for single-chip radios in nanoscale CMOS have yet been reported for that traditional approach, their scaling effectiveness is yet to be seen. It means that the majority of the area is occupied by the digital logic and memory in order to implement the digital baseband together with various controller and application 44 R. For this reason, the logic and memory determine the technology choice and it is rather not favorable to the linear RF operation.
When combined with TI's competitors' products also having embraced these principles, it appears that Digital RF is now the predominant architecture found in entry-level and feature cellular phones. The receiver [20] employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The antenna RF input signal is amplified and converted into the current domain by a low noise transconductance amplifier LNTA. The signal is then filtered and converted into the digital domain for further conditioning.
A digitally-controlled crystal oscillator DCXO generates a high-quality basestation-synchronized frequency reference such that the transmitted carrier frequencies and the received symbol rates are accurate to within 0. Various calibration and compensation procedures are exercised to keep the transceiver performance at optimum irrespective of the process and environmental conditions.
One such example is a periodic "just-in-time" compensation of the DCO gain variations [21]. The embedded processor [23] handles various TX and RX process calibration, voltage and tem- perature compensation, sequencing and lower-rate datapath tasks and encapsulates the transceiver complexity in order to present a much simpler software programming model. Since TI was years ahead of anyone else in researching this area see Sect. The situation nowadays, however, is entirely different.
This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit. Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio [Kenichi Okada, Shouhei Kousai] on www.farmersmarketmusic.com *FREE* shipping on.
A great majority of the newly 46 R. Script Processor communicates with the digital baseband processor and oversees the entire RF transmitter and receiver functionality Table 3. Leipold 6,, R. Leipold 6,, D. Staszewski 6,, R. Maggio 6,, R. With the total count of a few hundreds, the Digital RF IP ownership is now mostly spread around the world.
This is an indication of a dynamically growing and very healthy industry and parallels the historical development of IC chip. Even though TI invented the IC chip and held the fundamental patents, it obviously did not hurt its fantastic commercial growth. In fact, only a small minority of the patents related to IC nowadays belongs to TI. The FREF source is usually built as a tunable crystal oscillator, which features an excellent long-term accuracy and stability.
Due to relatively high cost of resonating crystal slabs, which are also bulky and require special packaging, there undergoes an intensive research for solid-state alternatives, such as RC-based oscillators with accurate temperature compensation as well as MEMS-based resonators. To the author's best knowledge, these emerging solutions are not yet mature enough to replace the decades-old proven crystal-based solutions in volume production of consumer products. In older process technologies, the frequency synthesizer has been traditionally based on a charge-pump PLL [2], as shown in Fig.
Also, the loop filter capacitor needs to be large to suppress reference spurs of the charge pump.
If realized as a metal-insulator- metal MIM capacitor, its size could be prohibitively large. MOS capacitors offer about 10 times area density improvement but the leakage current, which is due to gate electron tunneling, is getting worse with each process node. The leaky capacitor would introduce an equivalent parallel resistance whose value strongly depends on temperature, thus changing the loop characteristics. Efforts have been made to extend the architecture's lifetime by, for example, replacing the loop filter capacitor with a digital integrator or accumulator [24].
Since the capacitor's input and output are analog, the replacing accumulator needs to be preceded by an ADC and followed by a DAC. Moreover, the charge-pump PLL architecture suffers from high level of reference spurs generated by the correlative phase detection method, which require better filtering and thus slower loop transients that degrade frequency-settling times.
To relax this tradeoff, a fractional-Af PLL architecture with EA dithering of the clock division ratio is often used but at a cost of higher quantization noise. Furthermore, ensuring wide linear tuning range of a VCO is very difficult in low- voltage technologies [10] The new ADPLL [10, 11] frequency synthesizer architecture that is amenable to the scaled CMOS technology and is free of the above problems is presented in Fig.
It is built from the ground up using digital techniques that exploit the new paradigm described in Sect. It truly operates in the phase domain, which was first proposed by Kajiwara and Nakagawa [25]. This is in clear contrast to the traditional charge-pump PLL architecture, in which the phase domain operation is only a small-signal approximation under the locked loop condition [2].
The frequency reference information is wholly contained in the transition times i. Of the two possible transition types, only rising clock edges are used here. Likewise, the timing information of the high- frequency variable clock CKV is contained in its rising edge timestamps. For the sake of illustration, the frequency command word FCW , denoting the expected frequency multiplicative ratio, is 3.
Since the oscillation time period is an inverse of the oscillating frequency, there will be 3. Also, we assume the initial phase to be zero i. Hence, the reference phase signifies the expected number of CKV cycles from the time zero i. The phase error then adjusts the DCO frequency and phase in the negative feedback manner. A small inconsistency in the reasoning logic might possibly be noticed here.
Despite this apparent paradox, the system works properly since the error correction mechanism is the difference between these two phase quantities. As an example, the phase error needs to go higher i. The DCO shows not a single but actually three tuning word inputs to separately control the three varactor banks: The acquisition bank "A" performs channel selection by quickly settling to the neighborhood of the desired frequency. The tracking bank "T" is the one actually used during the mission-mode transmission or reception.
The attenuator factor a establishes the PLL loop first-order filtering characteristic: The final value of a was chosen to be the best tradeoff between the phase noise of the reference input and the DCO phase noise during the transmit TX and receive RX operations. It switches the PLL 52 R.
It is based on an LC-tank with a negative resistance to perpetuate the oscillation - just like the traditional voltage-controlled oscillator VCO on Fig. However, there is a significant difference in one of the components: Each one can be placed in either high or low capacitative state. The composite varactor performs a digital-to-capacitance conversion DCC. Since the varactors, i.
The finest varactor step size made possible by the fine lithography is on the order of 40 aF i. This is equivalent to a fine control of about electrons leaving and entering the LC-tank. Unfortunately, this fine control is not sufficient for any commercial wireless standard, so dithering is used that improves the time- averaged capacitative resolution. The tuning control is split into several banks of varying degree of frequency step size and range: The d frequency range is the largest since it has to cover all the frequency bands and margin for the oscillator variability.
In agreement with the Sect. The current is set through automatic calibration at a minimum value at which the oscillator still produces acceptable RF phase noise. The fine frequency resolution is achieved by EA dithering of its finest unit- weighted variable capacitors varactors using the high-speed down-divided DCO clock, as shown in Fig. The tuning word is a fixed-point number with the integer part directly controlling the number of active unit-weighted binary-controlled varactors.
The fractional part is fed to the EA modulator, which produces an integer stream whose average value is equal to that of the fractional input. The variable phase is a fixed- point digital word in which the fractional part is measured with a resolution of an inverter delay less than 20 ps and lOps in nm and nm CMOS, respectively by means of the TDC core, as shown in Fig. Thus obtained bit TDC core output forms a 54 R. The integer counter of DCO edges is not shown pseudo-thermometer code, which is then converted to binary and normalized to the CKV period, Ty, The number of inverters is set to cover one 7y.
To arbitrarily increase the dynamic range, the CKV edge counter with a sufficient wordlength is added, thus contributing to the integer part of the variable phase. In PLL applications, the absolute timestamps phase are more useful than the time difference instantaneous frequency. Because of the full digital nature of the phase error correction, sophisticated control algorithms through a dynamic change of the loop filter parameters refer back to Fig. Dynamic gear shifting of the ADPLL bandwidth to speed up the frequency settling [31] and to respond to unexpected and expected disturbances in the SoC, such as ramping up the power amplifier and DBB, keyboard or display activities.
Naturally, it is also amenable to the nanometer- scale CMOS technology. In the former, the analog quantity is the frequency deviation from the RF center frequency, whereas in the latter it is the RF amplitude or envelope. Transmit symbols, created from the user data, get pulse-shaped filtered in order to constrain the modulated carrier bandwidth to that of a given wireless standard. The modulation method is an exact digital two-point scheme, with one feed directly modulating the DCO frequency deviation while the other compensating for the developed excess phase error.
The DCO gain characteristics are constantly calibrated through digital logic to provide the lowest possible distortion of the transmitted waveform [21]. The DFC architecture will be described in detail in Sect. The number of active switches is controlled digitally and establishes the instantaneous amplitude of the output RF envelope. Fine amplitude resolution is achieved through high-speed EA transistor switch dithering. Despite the high speed of digital logic operation, the overall power consumption of the transmitter architecture is lower than that of architectures to date.
It has been proposed [10, 11] for RF wireless applications that require low amount of spurious tones and phase noise RF equivalent of jitter as well as low power consumption. The new architecture is based on a digitally-controlled oscillator DCO. Unfortunately, the free-running DCO would invariably exhibit wander or random walk of its phase with the expected variance approaching infinity [32]. Therefore, the DCO requires adjustment of its slowly varying wander lower frequency components of its phase noise with the stable frequency reference FREF.
The adjustments are obtained by forming a negative-feedback loop around the DCO. The higher 58 R. However, these components of a typical LC-tank oscillator can be made sufficiently low. As discussed above, it comprises a time-to-digital converter TDC to estimate the variable phase; an FCW accumulator to calculate the reference phase; an arithmetic subtractor to calculate the phase error based on the reference phase and variable phase; the loop filter to control the ADPLL bandwidth and transfer function characteristic.
It is realized as a two- point modulation scheme. One feed directly modulates the DCO, while the other feed is compensating and prevents the modulating data from affecting the phase error. Non-cellular transmitters typically have some additional constraints, such as coexistence with cellular host systems. To make the data sampling rate independent from fy and further push the replicas' energy beyond any protected frequency band, a new multirate architecture of Fig. This is natural since the FREF clock is the only source here that provides the long-term super-stable timing reference to correct the slowly drifting DCO phase.
Performing the phase error operations at a higher rate would not make sense. They are then merged with the modulating data of the same rate. Since their frequency relationship is a time-variant fractional number, their mutual interfaces require sampling rate converters SRC. The compensating path, on the other hand, can be as simple as the ZOH, which is mainly due to the low-pass transfer function of the reference phase accumulator. The second DCO divider shown in Fig. Note that the modulating data rate in Fig.
However, maintaining a harmonic relationship of the modulating clock rate to the DCO resonant frequency is highly beneficial to avoid injection pulling 60 R. The symbol rate processing in the digital baseband and the pulse-shape filtering, on the other hand, are preferably implemented in the fixed-frequency clock integer multiple of the symbol rate that is channel-independent. It implies that the FCW fractional number to the Fig. It is based on the Fig. In fact, FREF does not play any role in the data modulation. Consequently, the XO could be free-running and the reference frequency adjustment performed through FCW.
This way, the injection pulling spurs of the prior implementations [7, 8], with the input at FREF rate, are avoided. Staszewski Only a trivial multiplier of short computational delay is needed there. Hence it will not affect the ADPLL loop delay, which could worsen the phase margin in case of a wide bandwidth operation. The accurate multiplier now is only required in the feedforward transmit path, so adding pipelining delay stages should have no consequence on the system performance.
This would not be possible in the prior architectures without making hits or perturbations. The normalization adjustment of the DCO gain during the data modulation could be beneficial for faster settling, but it is necessary in case of a full-duplex operation, which allows no time for off-line adjustments. The direct calculation of the reference phase Rr [k] is in this case not needed. The only difference between these two forms is an arbitrary integration constant of the difference form.
Mathematically, integration following the differentiation is a unity operation except for the integration constant C. However, since the ADPLL typically operates in a non-integer-Af configuration, and the absolute phase of the communication path is never relied upon anyway, this effect is immaterial.
The practical benefits, however, are substantial. The differential form of the phase detector allows to "freeze" the time and to stop ramping the phase error, which is found useful during expected external perturbations, such as power amplifier PA ramp, a digital baseband DBB clock switchover or an external FLASH memory access. Since the phase error is an integral of the frequency error, a generally non-zero frequency error e.
Freezing the loop in order to avoid reaction to a transient but known perturbation is non-trivial in case of the direct-form phase detector. However, it only requires zeroing out the input of the final accumulator i. This feature was frequently relied upon during the field operation of the presented architecture. In the past, only subsampling mixer receiver architectures have been demonstrated: They operate at lower IF frequencies [41,42] and suffer from noise folding and exhibit susceptibility to clock jitter.
A recent study [43] uses a high sampling frequency of MHz after the mixer with an RC filtering stage to achieve sufficient programmability and flexibility for SDR receiver, which is presented in Chapter 4. In this architecture, discrete-time analog signal-processing is used to sample the RF input signal at Nyquist rate of the carrier frequency as it is then down-converted, down-sampled, filtered and converted from analog to digital with a discrete-time EA ADC. This method achieves great selectivity right at the mixer level. The selectivity is digitally controlled by the local oscillator LO clock frequency and capacitance ratios, both of which are extremely well controlled and precise in deep-submicron CMOS processes.
The discrete-time filtering at each signal-processing stage is followed by successive decimation. The main philosophy in building the receive path is to provide all the filtering required by the standard as early as possible using a structure that is quite amenable to migration to the more advanced deep-submicron processes. This approach significantly relaxes the design requirements for the following baseband amplifiers. Following the low-noise amplifier LNA , the signal is converted into cur- rent using a transconductance amplifier TA stage and down-converted into a programmable low-IF frequency by integrating it on a sampling capacitor.
After initial decimation through a sine filter response, a series of IIR filtering follows RF sampling for close-in interferer rejection. These signal-processing operations are performed in the multi-tap direct sampling mixer MTDSM that receives its clocks from the digital control unit DCU. The resampler follows and converts the sample rate from LO dependent clock rate to a fixed output rate of 8.
The final filtering is performed using a fully programmable tap channel select finite-impulse response FIR filter. One significance of this work is in demonstrating the feasibility of obtaining low noise figure in a receive chain in the presence of more than a million digital gates. Another significance is the development of very low-area, simple and highly programmable analog blocks that are controlled by software to guarantee the best achievable performance. A third significance is the architecture of analog structures that are amenable to migration from one process node to the next without significant rework.
Signal processing is used to reduce analog area and complexity. The radio solution was targeted to meet quad-band GSM specification in addition to supporting several experimental modes of operation.
The low-noise transconductance amplifier LNTA converts the received RF voltage vrf into igp in current domain through the transconductance gain g m. Since it is difficult to switch the current at RF rate, it could be merely redirected to an identical sampler that is operating on the opposite half-cycle of the LO clock, as shown in Fig.
In addition, a mechanism to prevent the charge overflow is needed. Both of these operations are accomplished by fixing the integration window length followed by charge readout phase that will also discharge the sampling capacitor such that the next period of integration would start from the same zero condition. The RF sampling and readout operations are cyclically rotated on both C s capacitors as shown in Fig.
When LOa rectifies N RF cycles that are being integrated on the first sampling capacitor, LOb is off and the second sampling capacitor charge is being read out. On the next Af RF cycles the operation is reversed. This way, the charge integration and readout occur at the same time and no RF cycles are missed. The sampling capacitor integrates the half-rectified RF current over N cycles.
The temporal integration of Af half-rectified RF samples performs an FIR opera- tion with N all-one coefficients, also known as moving-average MA , according to the following equation: Since the charge accumulation is performed on the same capacitor, this formula could also be used in the voltage domain. Its frequency response is a sine function and is shown in Fig.
It should be noted that this filtering is performed on the same capacitor but in the time domain, resulting in a most faithful reproduction of the transfer function. It should be emphasized that the voltage G v and charge G q signal-processing gains of the temporal moving-average TMA followed by decimation are merely due to the sampling time interval expansion of this discrete-time system the sampling rate of the input is at the RF frequency: In the following analysis, the RF half-cycle integration voltage gain of g", is tracked separately.
A "history" sampling capacitor Ch is added in Fig. When one of the Cr capacitors is being used for readout, the other is being used for RF integration. The IIR filtering capability comes into play in the following way: This time, the charge is shared on both Ch and Cr capacitors proportionately to their capacitance values. At the end of the accumulation cycle, the active Cr capacitor, that stores 1 — ci of the total charge, stops further accumulation in preparation for charge readout.
In other words, because of the charge conserva- tion principle, the input charge per sample interval is on average the same as the output charge. The voltage gain of the high-rate IIR filter is The input charge is cyclically integrated within the group of four Cr capacitors. Adding the redundant capacitors gives rise to an additional anti-aliasing filtering just before the second decimation of M. This could also be considered as equivalent to adding additional M— 1 zeros to the IIR transfer function in 3.
After the first bank of four capacitors gets charged Sai — Saa m Fig- 3. Ra and Rr in Fig. The readout and reset circuitry is not shown. It should be noted that after the reset phase, but before the sampling phase, the capacitors are unobtrusively precharged [40] to implement a dc-offset cancellation or to accomplish a feedback summation for the EA loop operation. Again, as explained before, the charge gain is due to the sampling interval expansion: It should be noted that it is possible to avoid aliasing of a very strong interferer into the critical IF band by simply changing the decimation ratio N.
The solid line is the composite transfer at the output of the spatial MA filter. The active element, the operational amplifier, does not actually take part in the IIR filtering process. It is merely used to sense voltage of the buffer feedback capacitor Cb and present it to the output with a low driving impedance.
This charge loss mechanism gives rise to IIR filtering. As stated before, the leak-out charge is not the output from the signal processing standpoint. The output charge Zk stops at the IIR-2 stage and does not further propagate, therefore it is of less importance for signal-processing analysis. Consequently, the voltage gain of IIR-2 is unity. The dc-frequency gain G v j ot in 3. The gain depends only on the g m of the LNTA stage, rotating capacitor value and the rotation frequency.
Amazingly, it does not depend on the other capacitor values, which contribute only to the filtering transfer function at higher frequencies.
The two FIR filters do not have appreciable filtering capability at low frequencies and are mainly used for anti-aliasing. It should be noted that the best filtering could be accomplished by making 3-dB corner frequency of both IIR filters the same and placing them as close to the higher end of signal band as possible.
The following equations describe the time-domain signal processing: However, for higher-order aliasing and overall system robustness, it has to be protected with a truly continuous-time filter, such as an antenna filter. A typical low-cost Bluetooth-band duplexer can attenuate up to 40 dB at MHz offset. The dc-frequency gains are G,,. The transfer function of these IIR filters is shown in Fig. The attenuation drops to 13 dB at 3 MHz. Within the 1 MHz band of interest, there is a 3 dB signal attenuation.
For the most optimal detector operation, this in-band filtering should be taken into consideration in the matched-filter design. This way, the main signal path is not perturbed. The feedback charge accumulation structure is 76 R. Each feedback capacitor Cf is associated with one of the two rotating capacitors of group "A" and "B". These two groups commutate the charging process. Voltage on the feedback capacitor can be calculated as follows. The charge depleted from Cf is dependent on the relative capacitor values.
Since the incoming charge is constant, the Qp charge will continue accumulation until the net charge intake becomes zero. However, a considerable portion of the overall RF-SoC fabrication cost is in its testing. The testing costs are high in case of a complex mixed-signal SoC for RF wireless applications involving extensive and time-consuming defect, performance, and standard compliance measurements. These factory measurements are tradition- ally made using expensive and sophisticated test equipment.
Furthermore, due to the complexity of the equipment and test settings, these measurements cannot be executed at-probe on wafer, before the IC chip is packaged, nor in the field after the chip leaves the factory environment. Consequently, it is desirable to improve testing costs and coverage during the complete life-cycle of an SoC in order to maximize wafer yield, profitability, and customer satisfaction.
Frequency synthesizers and transmitters are conventionally tested for RF per- formance and wireless standard compliance by measuring their output RF port for the correct carrier frequency, phase noise spectrum, integrated phase noise, spurious content, modulated spectrum, and modulated phase error trajectory see [22] for GSM while stimuli and control signals are applied.
The RF-BIST measurement method performs signal-processing calculations on a lower- frequency internal signal to ascertain the RF performance without external test equipment. This significantly saves test time and costs, and increases coverage. Several RF-BIST functions are now feasible with the all-digital transmitter and digitally-intensive discrete-time receiver. They include digital loop-back, mixed- signal feedback loop for dc offset cancellation and TX-RX RF loop-back at the mixer. Coupling at the package can be used to realize an external TX-RX feedback loop that incorporates the entire transceiver.
This loop can be used to perform several calibration and test functions. DPA is a digitally-controlled amplifier Despite the "all-digital" classification of the Fig. Consequently, in order to maintain the precise transfer function characteristic, the process, voltage and temperature PVT -dependent conversion gain of these blocks needs to be tracked and compensated.
Also shown is a tightly-coupled embedded RISC processor [23] that provides various types of digital assistance. This ensures that the ADPLL loop bandwidth is known accurately and the modulation transfer function is flat from dc to half of the sampling frequency. The embedded processor is used to accomplish this normalization using an on-line LMS algorithm described in [21]. The embedded processor is also used to reduce the overall current consumption while maximizing the RF performance [23].
The parameter of interest to which the DCO current and voltage need to be adjusted is the overall close-in RF transmitter performance captured in such metrics as the modulation spectrum, as well as rms and peak of the phase trajectory error PTE , in case of GSM. These measurements are fairly complicated and require the use of an expensive external test equipment connected to the RF TX output port.
At best, they can be used in factory to calibrate for the process changes but they simply rule out compensation for environmental conditions. The novel approach proposed in [19] solves the problem by calculating statistics of an internal signal, i. In this method, the FFT, rms and peak of the digital phase error samples are processed by the internal processor in real-time to estimate the phase noise spectrum, and rms and peak of the PTE, respectively, at the RF output.
The calculated statistics are then compared directly against the GSM specifications. For example, the max. DCO bias current of 18 mA in [12] can be reduced to as low as 6 mA if the wafer process is not weak and the die temperature is not high. It was driven by the desire to exploit the increasing power and affordability of CMOS technology for the purpose of reducing the wireless solution costs through system-on-chip SoC integration. It was found that implementing the traditional RF circuits in more and more advanced CMOS would make its performance increasingly worse, so the new RF architectures and design approaches had to be invented.
The transformation of the RF transceiver functionality into the novel time-domain operation, as embodied by the time-to-digital converter TDC - and digitally-controlled oscillator DCO -based all-digital phase-locked loop ADPLL , and the discrete-time receiver exploiting sophisticated signal processing, such as IIR. Enter "Digital assistance of RF": The new approach has proven to be very successful in the commercial world by substantially R. Higher code setting results in a better phase noise but the improvement vanishes at the highest code levels reducing cost, form factor and current consumption while increasing production yield and time-to-market.
Cambridge University Press, Still no longer an oxymoron," Proc. Vemulapalli, V Zoicas, C. Larson, T Murphy, D. Huang, "Digitally-synthesized loop filter circuit particularly useful for a phase locked loop," US patent 6,,, issued Oct. Solid- State Circuits, vol. Leipold, K Muhammad and P. T Balsara, and R. Muhammad, T Murphy, and R. RF, analog, baseband and software," Proc. Article ID , 14 pages, Staszewski, "Direct RF sampling mixer with recursive filtering in charge domain," Proc.
Hung, "Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver," Proc. Kostamovaara, "A low noise quadrature subsampling mixer," Proc. Lee, M Mikhemar, W. Every six months approximately, a new use for wireless appears, often leading to a new standard. Manufacturers of mobile handsets have a hard time keeping up, because the end user wants to access an increasing number of services from a single handset, and have it adapt to global roaming.
In the face of this proliferation a universal software- defined radio SDR which can communicate over all bands and standards is in high demand. A CMOS prototype implementation which covers the 0. Main circuit blocks of this SDR-RX including the programmable anti-aliasing analog filter, wideband LNA and high linearity harmonic-rejection mixer are presented.
Finally the areas where further performance improvement is needed are highlighted. Since then, considerable progress has been made on the digital front- end, digital baseband modem , protocols and the networking layers sections []. However the radio front-end and particularly the handheld equipment side has made less progress because of the many challenges involved. Essentially RF and analog blocks are almost always custom designed and have the least degree of flexibility. This heavily digitized radio concept provides the highest degree of reconfigurability.
It can transmit and receive many channels concurrently, and it has been attractive for cellular base-stations, enabling them to support multi-carrier waveforms. In this radio, the HF antenna is followed by a MHz lowpass filter to limit the input signal total dynamic range Fig. With this filter, any blocker above Extensive use of the cascaded integrator comb CIC titers for downsampling of the zero-IF signal is highlighted the symbol rate of that channel Fig. It is educative to note that this work uses cascaded integrator comb CIC filters.
CIC filters are usually the primary choice for decimation filtering, because their sinc f -shaped response nulls all the aliasing components. To better understand the consequences of this limitation, let's consider that the carrier frequencies as high as 6 GHz and protocols such as GSM have to be covered in a typical civilian use SDR-RX. Using the following equation this translates to about 12 Nyquist rate bits: Given today's state of the art and the resolution progress rate of 1. Furthermore, following the guidelines set in [13] it is estimated that power consumption of such ADC could be about W.
This is clearly a major obstacle in implementing the Mitola's SDR for portable civilian use receivers. To break this lock, the Toshiba dualband R. The entire band is first digitized and then a flexible digital front-end tunes to the individual channel of interest SDR-RX [14] utilizes mixers to downconvert the carrier frequencies of the PCS 1. This is in fact one step closer to conventional narrowband direct-conversion RX architectures [15], however what makes this architecture different from conventional thinking is that its inventors move most of the remaining usual analog blocks to the digital domain.
The entire band of interest, consisting of at least 50 channels about 10 MHz is digitized in one piece. Then the digital front-end performs further downconversion, channel selection and the decimation tasks to tune to the desired channel. Analog front end consists of two RF band-select filters for two bands: It should be noted that this is a low IF architecture with a variable IF frequency per channel. No image rejection filter is used and thus the typical required image rejection e.
More importantly since one RF band select filer is needed per each band, this approach quickly becomes impractical if large number of bands is targeted, as is the case in SDR. At this stage the solution is either to design the programmable RF band select filters or to entirely remove the RF band select filter. They proposed to construct a programmable RF filter using the mixer multiplier as part of a sampler and weighted integrator Fig.
Although Poberezhskiys originally used different terms, we refer to this combination as weighted windowed integration sampler or in short windowed integration sampler WIS. By shifting the window and repeating the multiplication-integration, output samples at any sampling moment nT s can be calculated. This operation is formulated as follows: This equation can be rewritten as: Thus a more familiar interpretation of WIS can be represented by Fig. Now it is clear that the continuous time input, x t , is filtered by a continuous time filter prior to being sampled. This is how WIS implements a sampler with built-in filter.
The filter has a finite impulse response given by w —t or equivalently a frequency response of W f. Poberezhskiys [16] approximated w t by a discrete waveform generated by a digital weight function generator WFG. Sampling rate can also be set to be lower than the RF signal Nyquist rate, and thus the sampled output is downconverted due to subsampling process [10]. This is 90 R. V 0J , n f s 2f, 3f, f a very powerful concept, but due to circuit imperfections satisfying the requirements of a wireless receiver with no RF preselect filter remains impractical [12].
Let's have a closer look to how baseband- WIS can be used in a wireless receiver. As explained before the finite impulse response of the filter is given by w — t and thus the RWIS built-in filter transfer function, in frequency domain, is given by 4. It has zero response for those input frequencies residing at integer multiples of the sample rate, f s. If the channel of interest properly lies at DC or its vicinity all the aliasing interferers will be around the nulls at Nf s and strongly suppressed prior to sampling.
In other words one must choose a sample rate higher than the minimum required by Equation 4. Other interferers, which are located in the side lobes but not on the nulls vicinity, are attenuated moderately and then fold down to the main lobe but away from the wanted channel at DC Fig. With the above description, it is clear that RWIS with its programmable built- in antialiasing filter fits very well into a wireless receiver to replace traditional impulse samplers. However, if all the anti-aliasing attenuation must be provided by the RWIS, it requires impractically high sample rates.
Beside this impractical rate, circuit imperfections also limit the achievable null depths to around 50 dB [19]. Let us continue by highlighting that Mitola's SDR is by definition capable of receiving and transmitting multiple channels concurrently. In other word all the channels are digitized and available to the DSP at once, and the DSP can arbitrarily select any number of the channels per user request. This may be of interest to the military users but it is usually impractical and overkill with resulting increase in complexity and power consumption for portable civilian use cases.
In civilian use of a personal communications device, the user knows beforehand what service he wants. Thus we find it more suitable to define the SDR as a radio platform which can be programmed to receive or transmit any single channel, with any modulation and located anywhere in a broad but finite predefined band. If two or more channels need to be received concurrently, then two or more of our type of SDR could be used in parallel with a possible sharing of some blocks.
The required SDR-RX flexibility must be offered at the low cost and low power consumption similar to those of the traditional narrowband receivers. The key points to low power narrowband design lies in the pre- ADC analog blocks acting as signal conditioner and delivering a well conditioned low dynamic range signal to the ADC Fig.
On the other hand removal of the preconditioning blocks in favor of providing flexibility, in Mitola's SDR-RX, results in impractical ADC requirements with high power consumption.